6502 Video Adapter

The counters consist of a set of six 4-bit counter ICs arranged into two 12-bit counters for the rows and the columns. They’re 12 bits each because they count the pixels at the VGA mode level: including the blanking periods, that’s 800x525. I only need 10 bits for each of these, but counters come 4 bits at a time…​

One thing I did to fix the timing issues with Ben Eater’s video card was to try to use flipflops instead of latches for everything (it makes proving the timing compliance of everything easier). Because of this, everything on the board except for the 6502 interface is in a single clock domain driven by the pixel clock, and the logic of counting is controlled by enable and clear inputs instead of gating the clock and resetting asynchronously. The column counter is always enabled, and its clear and the row counter’s enable and clear are controlled by the sync generation.

I think the biggest limitation with Ben Eater’s design is that it only allows writing to the VRAM during the blanking period, because the rest of the time the video adapter needs to read from it. I solved this using double-bufferring: there are two separate VRAM chips (which I call the "buffers"), one of which is attached to the computer’s memory bus for drawing, and the other is attached to the row and column counter for displaying. Then, once the computer is done drawing a new frame, the buffers are swapped and the newly drawn buffer is read from and displayed to the screen. The swapping in this case is done by a set of three 74CBT16390 "bus switches", which are pretty much just giant, bidirectional multiplexers.

The row and column are turned into an address by basically just doing addr = {row[8:2], col[9:2]} - since the lower 2 bits are skipped, it divides the "native" VGA resolution by 4 to get 160x120.

Also attached to the memory bus is the control register. This is necessary for controlling the buffer swap, but also for another reason: the address space the board gets is not large enough to address all of its VRAM! Due to limitations of the 6502, I can’t give the card the complete 15-bit address space it needs, just 14 bits. To work around this there’s another bit in the control register to set the high bit of the VRAM address being accessed by the computer (this is like a typical "bank switch" control). While the card needs this much address space in order to do its row/column addressing nicely, there’s a lot of unused space within it (each row is given 256 bytes of address space, but they’re only 160 pixels long). This lets me implement the control register by just checking if the computer is writing to the first byte past the end of a row, piggybacking off of my existing address decoding.