Brainfuck CPU

You can access the design files for this project here. They’re not very good, though (I didn’t exactly know Verilog when I started…​)

In Spring 2023, I had a very exciting opportunity: CMU began offerring a new tapeout course, with minimal prerequisites, which would give me the chance to design and tape out my own chip! There were just two problems though: I didn’t know Verilog yet, and I didn’t really know what I wanted to make.

I was taking Intro to Digital Systems at the same time (which would later be made a prerequisite for the course), which would teach me Verilog, but the question of what chip to create was more elusive. After much waffling over potentially making an ASIC version of the computer Ben Eater builds in his 8-bit Computer series, I eventually decided that it would be more interesting to create a new design of my own, and in search of some architecture that would be simple enough for me to implement with my then-limited knowledge of computer architecture, and also small enough to fit in the small chip area given to us by the course, I eventually settled upon Brainfuck.

For those who don’t know what Brainfuck is, it’s probably the most notable example of an "esoteric" programming language - a programming language not designed to be useful, but to be somehow weird or funny or both. Brainfuck programs consist only of 8 different single-character commands +-<>.,[], which allow for doing "arithmetic" (only incrementing and decrementing by 1), looking at different bytes of memory (only moving by 1 at a time), printing and reading single bytes from I/O, and looping. There’s no way to do normal arithmetic or do any other kind of construct other than through these 8 commands…​ so any programs end up looking pretty incomprehensible, and doing anything interesting is difficult. However, one thing that is simple about Brainfuck is implementation of the language itself - I realized that while in the realm of programming languages we refer to Brainfuck’s operations as "commands", but they could easily be equivalently imagined as instructions for a super duper garbage CPU. So that’s what I set out to implement, armed with around half a semester of Verilog by this point.

The design I ended up creating that semester was mainly inspired by Ben Eater’s computer, mixed with the simple "RISC-240" CPU from Intro to Digital Systems. It’s heavily FSM-driven, and is extremely clock-inefficient (each memory operation including fetches take 4 cycles, and the ] instruction takes something like 8 cycles at minimum not counting memory)

And, well, it worked! The course thankfully required us to do an amount of verification on our designs before we taped out, and when I finally received my chip more than a year later (man…​.) I was able to run all the same test programs as I did on FPGA!