Boulder, CO / Pittsburgh, PA
Master of Science in Electrical and Computer Engineering, May 2026 (expected)
Bachelor of Science in Electrical and Computer Engineering, May 2025
Relevant Courses: Computer Architecture, Embedded Systems, Logic Design+Verification, PCB Design, FPGA/ASIC Chip Design
On DV tooling team, developed new tool for bridging simulator processes into a single simulation via inter-process communication
Implemented in C++, SystemVerilog, and Python, using the SystemVerilog DPI interface
Tool allowed DV team to bring up difficult internal IPs in new simulation environment
On random instruction generator team, created new program for detecting complex patterns in generator outputs
Used C++, SystemVerilog, and Lua plus extensive computer architecture knowledge
Software quickly adopted by multiple CPU teams in order to improve random generator quality and development speed
Improved HackerFab’s lithography stepper’s vibration susceptibility, reducing positional deviation to 1.8 micrometers
Created initial design for custom DLP projector (PCB and optical design) to improve stepper reliability and usability
Wrote firmware and designed custom PCB for ultra-low-power watch with GPS map and tracking, on team of 3
Firmware written in embedded Rust for STM32 microcontroller, PCB designed in KiCad and fits 60+ components in 50x40mm area
Final design iteration: 1 week battery life with GPS tracking (unlimited with solar charging!) in normal sized watch
Team was awarded first place out of 44 teams at project demo by capstone judges
Designed a minimal-instruction-set CPU which implements an 8-instruction esoteric programming language, using SystemVerilog
Verified in simulation with CocoTB, validated in hardware thru synthesis on iCE40 FPGA, and taped out on Skywater 130nm process
Built a 160x120, 256 color VGA graphics adapter for a DIY 6502-based microcomputer which I also built
Designed adapter out of discrete 7400-series logic gates, verified in SystemVerilog, and constructed on a custom PCB
Implemented a 6-stage pipelined RISC-V CPU core using SystemVerilog on team of 3 for Computer Architecture class
Due to unique cache design used to meet design constraints, design was Pareto-optimal out of 29 teams in class
Wrote firmware and software for a remote-controlled solar-powered land-based rover, on team of 4
Used C++, Python + asyncio, and Rust languages, communicating over 4G cell and serial
Fabricated a costume head using 3D printing and vacuum forming, which displays dynamic images and animations on LED matrices
Wrote customizable firmware in C++ for Teensy, loading images and animations from an SD card
As club sysadmin ("Root"), revamped club website, mail hosting, project hosting, and member management infrastructure
Reorganized club network architecture to be in line with modern standards
Programming Languages: C, Rust, x86/ARM/RISC-V Assembly, C++, Python,
Kotlin, Java, C#, HTML, CSS, JavaScript, SQL, MATLAB
Hardware/Embedded: Verilog/SystemVerilog, FPGAs, Microcontrollers (Arduino,
Teensy, RP2040, STM32, CH32), FreeRTOS
Software: Linux/Unix, Windows, Git, Perforce Helix, Solidworks, Fusion 360,
KiCad, Blender, Godot Engine, Unity Engine, QGIS
Fabrication: PCB design, Machining, CNC / CAM, 3D printing, Laser cutting